Various types of data adaptors have been designed in the past primarily for the purpose of rendering one data processing network to be compatible with another data processing network. For example, U.S. Pat. No. 4,549,177 to A. W. Warburton discloses a precision fathometer interface adaptor that enables computerized oceanographic surveys of both shallow and deep water depths to be conducted at the same time from a surface vessel. The adaptor is generally made up of a series of five 4-bit flip-flop latch devices, a series of four quad-two multiplexers, a series of five dual data bus controllers and a 16-bit parallel byte computer. A gate control and mode selection device is interconnected to the latch devices, multiplexers and controllers for controlling the admission of 16-bit and 20-bit parallel data sensor sources and for converting the 20-bit parallel data sensor source to 16-bit parallel data sensor source all for ultimate processing by the computer. U.S. Pat. No. 4,481,514 to J. M. Beukers et al relates to a microprocessor based radiosonde or a balloon launchable high altitude, round trackable and gravity descending atmospheric parameter measuring device. The atmospheric measuring device is generally made up of a multiplexer for receiving atmospheric parameter-sensor inputs, an analog-to-digital converter, a miroprocessor, a radio transmitter and an ascent/descent control switch for the microprocessor. In response to the control switch, the microprocessor controls the multiplexer as to when the multiplexer can transmit sensed atmospheric parameters for processing and transmission in a serial digitized data stream to a ground station. U.S. Pat. No. 4,617,624 to J. B. Goodman concerns a peripheral memory apparatus for a central processor unit (CPU) where the apparatus has more than one operative mode configuration. The apparatus is generally made up of a CPU information bus, a pair of data input/output (I/O) buffers, and address buffer, an address select logic device, a controller, a pair of memory banks and a data source arrangement. The data source arrangement is operatively associated with the controller, the memory banks and the data I/O buffers. Depending on the operation of an address-logic controller, a memory bank is addressed directly or indirectly for removal of data to the CPU bus.
However, none of the aforediscussed references were remotely concerned with an improved parallel-to-serial-data interface-adaptor that is readily and preferably connectable to at least two parallel 32-bit data inputs. Moreover, the adaptor is operable to selectively process either one of the two parallel data inputs when received and then is further operable to convert any processed data input into a serial data stream as an output to a serial data processor and the like for subsequent processing. Once the adaptor is initialized and by reason of the adaptor being of master/slave configuration, it can handle separate parallel data inputs in selective fashion without requiring manual or operator assistance in processing either parallel input to a predetermined configuration and then converting any processed data input to a serial format output that is compatible with a serial data processor.